FIG. 1 is a block diagram of a conventional digital demodulation stage, e.g., as described in French Patent Application No. 93 00051 filed on Jan. 6, 1993.
A received signal referenced SR and constituted by a quadrature modulated signal is applied to the input of an intermediate frequency band-pass filter 10 followed by two multipliers 11 and 12 which multiply the signal output from the filter 10 by two signals in quadrature. One of these signals is output directly from a local oscillator 13, and the other signal is output from a .pi./2 phase-shifter 14. The local oscillator 13 generates a signal having the same frequency as the center frequency of the received signal SR. The output signals from the multipliers 11, 12 constitute two base-band components I and Q. These components are applied to anti-aliasing low-pass filters 15 and 16 followed by analog-to-digital converters 17 and 18 supplying respective digital components XF and YF, e.g., quantized into 6 bits. The converters 17 and 18 are followed by Nyquist-root low-pass filters 19 and 20 whose outputs are applied to a clock recovery module 21 supplying a clock signal H driving the converters 17 and 18. Carrier recovery apparatus 22 constituted in the above-mentioned application by phase-setting apparatus also receives the components XF and YF.
The function of the phase-setting apparatus 22 is to rotate the constellation of phase states of the received signal as a function of data representative of the difference in angle of the constellation. Apparatus 22 supplies two digital data trains In and Qn constituting a received symbol at each symbol time Ts. The position of each symbol in the constellation is defined by its coordinates XF and YF obtained by quantizing the analog data trains I and Q.
Apparatus 22 may optionally supply the digital trains In and Qn to detection apparatus 23 for detecting carrier frequency loss, such as the apparatus described in French Patent Application No. 93 15086 filed on Dec. 15, 1993. Other types of detection apparatus may also be used for detecting carrier frequency loss.
The components In and Qn are also applied to a decision member 24, enabling a symbol to be associated with each pair of phase-set components. Member 24 is followed by ambiguity removal apparatus 25, making it possible to remove the uncertainty resulting from decision-taking and thus to determine the correct symbol.
Carrier recovery must be performed in particular when starting up a modem. Various solutions are suitable for implementing the carrier recovery apparatus 22. The drawbacks with existing analog solutions are that they require adjustment, and that certain parameters drift with temperature.
Digital solutions are preferred since they do not suffer from those drawbacks, and they offer the advantage of being more stable and reliable. An entirely digital known solution for implementing the carrier recovery apparatus is described in French Patent Application No. 93 00051. That solution uses a phase-locked loop such as the loop described with reference to FIG. 2.
FIG. 2 shows a phase-locked loop performing the function of the carrier recovery apparatus 22 of FIG. 1.
The components XF and YF, e.g. quantized on 6 bits, are applied to a correction module 30 for rotating the constellation of the phase states of the received signal SR as a function of data sin.theta.c and cos.theta.c representative of the difference in angle between the ideal constellation and the constellation of the phase states of the received signal SR.
In the phase plane, this is equivalent to rotating the vector whose digital quadrature components XF, YF are those obtained at the outputs of the low-pass filters 19 and 20 of the demodulation stage. The components In and Qn of the vector resulting from this rotation are associated with a point that coincides with one of the points of the constellation of the ideal phase states.
The correction module 30 multiplies the pair of components XF and YF by a rotation matrix whose different sets of coefficients are stored in a memory module 31. The components In and Qn output by module 30 are applied to a phase error detector 32, making it possible to estimate the instantaneous phase difference between two successive pairs of components XF and YF, and supplying a phase error referenced E, where: EQU E=In.Qn.(In+Qn).(In-Qn)
This phase error E may also be written as follows: EQU E=.rho..sup.4 sin4.alpha.
where (.rho., .alpha.) are the polar co-ordinates that correspond to the Cartesian co-ordinates (In, Qn). This error E cancels for .alpha. .epsilon.{.pi./4, 3.pi./4, 5.pi./4, 7.pi./4}, i.e., when there is no rotation of the constellation.
The phase error E is supplied to a loop filter 33 of the low-pass type (of second order in this example) including two processing paths 34 and 35. The first path 34 includes an attenuator 36 which divides the phase error E by a coefficient Gd so as to supply a result Rd. The second path 35 includes an attenuator 37 which divides the phase error E by a coefficient Gi. For example, the coefficients Gd and Gi represent division by integer powers of two. The phase error is applied to a phase accumulator constituted by a summing circuit 38 followed by a bistable circuit 39 sequencing the operation in time with the symbol time Ts. The output of the bistable circuit 39 is looped back to the summing circuit 38 and supplies a result Ri.
The results Rd and Ri of the processing performed by the two paths 34 and 35 are applied to a summing circuit 40 so as to supply a filtered phase error indicator EF.
By appropriate choice of the gains Gi and Gd, the filter 33 makes it possible to suppress noise and in particular phase jitter.
The filtered phase error indicator EF is applied to a phase accumulator 41 comprising a summing circuit 42 followed by a bistable circuit 43 operating at the symbol time Ts. In this way, the filtered phase error indicator EF of the successive received symbols are totalled in the phase accumulator 41. The result of the totalling is angular difference data .theta.c enabling the correction module 30 to bring the constellation of the received signal SR back into the appropriate position for subsequent decision-making.
The tracking range of such a phase-locked loop is determined by the size of the summing circuit 38, which is the number of bits in the summing circuit (e.g., 8 or 16 bits), and is therefore set for a given throughput.
The acquisition range is determined, in particular, by the gains Gi and Gd. These gains are adjusted such that the loop bandwidth is narrow, so as to suppress noise, but the acquisition range is then narrow. When the detection apparatus for detecting carrier frequency loss detects loss of carrier recovery synchronization, it is necessary to modify the gains so as to increase the acquisition range, thereby enabling the carrier frequency to be recovered. Unfortunately, the apparatus is then more sensitive to noise, and the error rate deteriorates.
Carrier frequency recovery needs to be performed in particular at the start of a call, and this poses a problem when the symbol rate is low because, in that case, the frequency difference to be made up by correcting the phase of the constellation might be greater than the acquisition range.